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CXL1008M/P
CMOS-CCD Signal Processor for Skew Compensation
Description CXL1008M/P are CMOS-CCD signal processors developed for the variable-speed video signal processor for home-use 8mm VCRs. Features * Low power consumption 105mW (Typ.) * Built-in peripheral circuit * Adjustment is necessary for one part. Structure CMOS-CCD Functions * 1/2H 359-bit, direct 20-bit CCD register * Clock driver * Timing oscillation circuit * Automatic bias circuit * Sync tip clamp circuit * Dummy VD insert circuit * Sample/hold circuit Absolute Maximum Ratings (Ta = 25C) * Supply voltage VDD 11 V VCL 6 V * Operating temperature Topr -10 to +60 C * Storage temperature Tstg -55 to +150 C * Allowable power dissipaiton PD CXL1008M 500 mW CXL1008P 1000 mW Recommended Operating Conditions Supply voltage VDD 9V 5 VCL 5V 5 CXL1008M 28 pin SOP (Plastic) CXL1008P 28 pin DIP (Plastic)
% %
Recommended Clock Conditions * Clock input amplitude VCLK 0.15 to 1.0 (0.3 Typ.) * Clock frequency fCLK 10.738635
Vp-p MHz
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E60248-PS
CXL1008M/P
FEED OUT
SIG DELAY
Block Diagram
AUTO
CCD OUT
13 AUTOBIAS CIRCUIT
SIG IN2
24
25 23
21 12
19
1/2H
SIG IN1 11 D T10 28 T9 27 SKEW IN 26 SKEW 1 2
OUTPUT CIRCUIT 50mV 50mV REFERENCE OUTPUT CONTROL
SIG OUT
10 MUTE IN 17 16 JOG IN EXT VD T8 15 9
FEED IN
T1
2 DUTY CONTROL
DRIVER TIMING GENERATOR
T7
T2
3 4 5 6 1 18 14 20 7 22 8
T4
REC/PB
CLK IN
T3
T5
Pin Configuration (Top View)
VDD
VSS
VSS
VCL
T8 15 EXT VD 16 JOG IN 17 VSS 18 SIG OUT 19 VDD 20 SIG DELAY 21 REC/PB 22 CCD OUT 23 FEED OUT 24 FEED IN 25 SKEW IN 26 T9 27 T10 28
14 13 12
VCL AUTO SIG IN2
11 SIG IN1 10 MUTE IN 9 8 7 6 5 4 3 2 1 T7 T6 CLK IN T5 T4 T3 T2 T1 VSS
-2-
T6
CXL1008M/P
Pin Description Pin No. 1 7 10 Symbol VSS CLK IN MUTE IN I I 0.3Vp-p I/O Supply voltage GND Input the sine wave of 3fsc (10.738635MHz) > 50k > 100k Description Impedance ()
The video signal mute is generated at High level. 5V when See the Logic Table of Signal Output Selection muting, normally 0V State (Table 1). 1.1Vp-p or less 2.2Vp-p or less Signal input pin of CCD DL. Input composite video signal. Signal input pin of the through side. Input composite video signal. The DC level of automatic bias is output. +5V Power supply 1
11 12 13 14 16
SIG IN1 SIG IN2 AUTO VCL EXT VD
I I O
> 100k > 100k 10k
I
5V when VD Use this pin when VD is inserted to the video signal is inserted with the extrenal dummy VD signal input. JOG mode 5V PB/REC mode 0V JOG/NORMAL PB selection pin. See the Logic Table of Signal Output Selection State (Table 1). GND
> 100k
17
JOG IN
I
> 100k
18 19 20 21 22 23 24 25
VSS SIG OUT VDD SIG DELAY REC/PB CCD OUT FEED OUT FEED IN I I O O I O +9V
Final output Power supply 2 After the output from Pin 23 CCD OUT passes through LPF, input it to the same pin and insert clamp and VD. 5V when PB Operate the clock at High when PB. 0V when REC Stop the clock at Low when REC. Direct output from CCD DL Feedback DC output Smoothing capacitor connection pin of the bias commutation loop on the output circuit Select Direct DL and 1/2H DL signals when High and Low, respectively. See the Logic Table of CCD DL Mode Selection (Table 2).
0.6 to 1.5k
> 100k > 100k 0.6 to 1.5k 10k > 100k
26
SKEW IN
I
> 100k
Note) T1 through T10 test pins must be connected as shown in the application circuit because of the IC internal circuit. Notes on Handling Countermeasures for electrostatics are necessary because some pins have low electrostatic strength (particularly Pin 26: SKEW IN).
-3-
Electrical Characteristics (See the Electrical Characteristics Test Circuit) (Ta = 25C, VDD = 9.0V, VCL = 5.0V, fCLK = 10.7MHz, VCLK = 0.3Vp-p sine wave) Switch Conditions Min. Max. 12 10 1.0 6.0 4.4 4.2 2.0 1.7 1.5 H H L H L L L L L H -55 -3.0 -1.2 -1.2 H H L -1.3 a a b b b b b c a c b a b b b g g g a b b b c c c L L L L L H L L L L L H H -3 -0.5 -0.5 H H L -0.2 H 0 0 0 2.0 0 0 -0.8 -0.8 0 -2 0 0 0 3 2 2 4.4 2.4 2.5 55 3.0 0 0 1.3 0 -- -- 0.2 10 4 4 mA mA V V V V V V mV dB dB dB % dB dB dB dB % % % 2 2 2 3 3 4 5 5 5 6 7 8 8 9 10 10 10 7 8 0.15 4.0 4.0 4.0 H L a a b b a a a a L L 5.0 4.2 0.3 Typ. Unit 1 2 P5 1 1 a a H c a a a a a a b b b b b b c a b b d b b b d b a f f a e e e e e e H b a c b Direct 1/2H c c b a Direct 1/2H c c b a 3.58MHz/100kHz 10MHz/100kHz 10MHz/100kHz Direct 1/2H at 3.58MHz c 1.1Vp-p input 2.2Vp-p input 2.2Vp-p input a H a H 3 4 5 P1 P2 P3 P4 PB, JOG c c Control Pin Conditions 1, 2 Note Test Conditions
Items
Symbol
Power current
IDD
ICL
Clock input level
CLK
Vdi1
Signal input pin voltage
Vdi2
Vdi3
Signal output pin voltage
Vdo1
Vdo2
CCD signal output voltage difference
Dab
-4-
IGCCD
Signal insert gain
IGIn2
IGDL
CCD output signal gain difference
Gab
fCCD
Frequency characteristics fIn2
fDL
Frequency characteristics fab difference
DGCCD
Differential gain
DGIn2
CXL1008M/P
DGDL
Items Test Conditions Max. 5 deg deg deg Vp-p 2.2 -- 65 65 0 4.0 -- 50 -- -- 100 -- 1.0 Vp-p dB dB dB mV V V 11 11 11 12 5 5 1.1 10 10 10 1 2 P5 0 3 3 3 -- -- 55 0 0 -- -- d H 50 50 50 L L L H H L L L d d a b g c H L L L H L L c c g g g g b a e a b f e b b f e b a g b b b b b a 3 4 5 P1 P2 P3 P4 1.1Vp-p input 2.2Vp-p input 2.2Vp-p input c a/b c b a 2Vp-p video signal from sync tip a a b c Min. Typ. Unit Note
Symbol
Switch Conditions
Control Pin Conditions 1, 2
DPCCD
Differential phase
DPIn2
DPDL
Allowable input amplitude
VIN1-AC
VIN2-AC
S/NCCD
S/N rate
S/NIn2
S/NDL
VD insert depth
VVD
-5-
Logical input
VIN H
VIN L
1 Control pins correspond to P1 through P5 of the Electrical Characteristics Test Circuit. 2 Symbols "H" and "L" in control pin conditions represent "VIN H" and "VIN L" of logical input.
CXL1008M/P
Electrical Characteristics Test Circuit
a OSCILLOSCOPE SPECTRUM ANALYZER x1 LPF 0.1 d BPF Note 2) P3 390k A2 24 20 10k 23 22 21 16 19 18 17 15 5V P2 NOISE METER 0.1 9V P4 x1 x1 VECTOR SCOPE 2k b SW4 SW5 Note 1) c x1 2k V2 2SA1175 220k a b V3 2SA1175 9V
10
P5
22
5V
28
27
26
25
[dB]
-50 5.8 10.7
[dB]
-6-
5 7 11 10 A1 5V P1 CLK a b c 5V SW1 0.1 8 14 10 12 100k 6 9 13 SW2 Note 2) BPF Frequency Response a 1M 0 -3 -50 0 50 200 4.1M 10.7M Frequency [Hz]
a b SW3
1
2
3
4
100kHz 1.1Vp-p SINE WAVE 100kHz 300mVp-p SINE WAVE c 3.58MHz 300mVp-p SINE WAVE 0.1 d 10MHz 300mVp-p SINE WAVE
V1
e b 20k VBIAS f g
GROUND 100kHz 2.2Vp-p SINE WAVE 5-STAIR CASE WAVE
Note 1) LPF Frequency Response (Delay Time to 140ns)
0 -3
0
CXL1008M/P
Frequency [MHz]
CXL1008M/P
Notes) 1) Current value when the clock is in operation in the PB or JOG mode. In the REC mode, the clock is stopped (Pin 22 is at low) to save power. 2) With the signal input pin voltage value, the video signal sync tip is clamped. 3) Vdo1 is a CCD OUT output voltage when the SIG IN1 input voltage is Vdi1. Vdo2 is a SIG OUT output voltage when the SIG IN2 input voltage is Vdi2. Vdo1 and Vdo2 represent outputs for the sync tip clamp level when a white level signal is input as shown in the diagram.
Output signal
Vdo
40%
100% 1.0Vp-p
Vdi
Input signal
4) Dab denotes an output voltage difference of CCD OUT when the direct DL and 1/2H DL are switched. 5) IGCCD is a CCD OUT gain when a 1.1Vp-p 100kHz sine wave is input to SIG IN1. Output amplitude (Vp-p) 1.1Vp-p
IGCCD = 20 log
It is measured by giving a Vdi1 + 0.6 bias with VBias. IGin2 and IGDL are SIG OUT gains when 2.2Vp-p 100kHz sine wave is input to each of SIG IN2 and SIG DELAY pins. Output amplitude (Vp-p) 2.2Vp-p
IGin2 = 20 log
It is measured by giving a Vdi2 + 1.1V bias with VBias.
-7-
CXL1008M/P
6) Gab is a gain difference between the direct DL and 1/2H DL. 7) It represents a loss at 3.58MHz compared with 100kHz. It is measured by raising the SIG IN1 input pin by 0.6V higher than the sync tip clamp level (Vdi1) with VBias.
3.85MHz 300mVp-p sine wave 100kHz 300mVp-p sine wave
SIG IN1 DC
VBias = Vdi1 + 0.6V
FCCD = 20 log
V3.58MHz output V100kHz output
8) It represents a loss at 10MHz compared with 100kHz. It is measured by raising the SIG IN2 or SIG DELAY input pin by 1.1V higher than the sync tip clamp level (Vdi2 or Vdi3) with VBias. 9) Fab is a frequency response difference between the direct DL and 1/2H DL. 10)
Chroma 40 IRE 140 IRE 1.1Vp-p at DGCCD 2.2Vp-p at DGin2 or DGDL 40 IRE 1H 63.5s
DG is measured with a vectorscope in each mode of the 5-stage waves. 11) Measure S/N of the BPF 100kHz to 4.2MHz in the subcarrier trap mode with a video noise meter. 12)
SIG DELAY Input waveform
EXT VD input
SIG OUT Output waveform
2Vp-p
VVD
Set a voltage value at VVD when inserting EXT VD to the 2Vp-p signal output waveform sync tip of SIG OUT.
-8-
CXL1008M/P
CLOCK
3fsc (10.738635MHz) Sine wave 0.15 to 1.0Vp-p
Function Outline Output signal selection
SIG IN2 (PB) SIG DELAY (JOG)
SIG OUT
50mV REF
The video output signal is selected by selecting the output switch for three signals: Pin 10 (MUTE IN), Pin 17 (JOG IN) and Pin 16 (EXT VD).
Table 1. Logic Table of Signal Output Selection State Input control signal state JOG IN 0 0 0 0 1 1 1 1 MUTE IN 0 0 1 1 0 0 1 1 EXT VD 0 1 0 1 0 1 0 1 PB O O x x x x x x Video signal output selection state JOG x x x x O x x x VD insert x x x x x O x O MUTE x x O O x x O O
Note 1) Figures "0" and "1" of the input control signal state are equivalent to "Low" and "High" of logic. Note 2) Items marked with the symbol "O" in the video signal output selection state are selected. Note 3) PB = JOG IN * MUTE IN JOG = JOG IN * MUTE IN * EXT VD VD insert = JOG IN * EXT VD MUTE = MUTE IN
-9-
CXL1008M/P
CCD selection
1/2H (359bit) SIG IN1 D (20bit) SKEW IN CCD OUT
Table 2. Logic Table of CCD DL Mode Selection Control signal SKEW IN 0 1 CCD DL mode D x O
9V 560 SIGNAL OUTPUT 10 10k 2k 18k 220p 270p
1/2H O x
Application Circuit
390 2.2k 4.7k 220 10 390 8.2k 1.8k 1k 1.5k 120 10H
220k SKEW IN
10 22 10k
0.022 REC/PB 1M
47
1000p
JOG EXT IN VD
220k 24 23 22 21 20 19 18 17 16 15
28
27
26
25
1
2
3
4
5
6
7
8
9
10 2M
11 2M
12 10
13 5V
14
47
1000p
100k
0.01F 3fsc 0.3Vp-p SINE WAVE MUTE IN 0.047 0.047 SIGNAL INPUT
Transistor to be used PNP: 2SA1175
510
510
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Frequency characteristics (Ta = 25C)
0
Gain [dB]
-1
-2
10k
100k f - Frequency [Hz]
1M
- 10 -
CXL1008M/P
Supply voltage (VCL) vs. Insert gain (IGCCD)
2 1
Supply voltage (VCL) vs. Frequency characteristics (fCCD)
fCCD - Frequency characteristics [dB]
5.25
1
0
IGCCD - Insert gain [dB]
0
-1
-1
-2
-2
-3
-3 4.75
5.00 VCL - Supply voltage [V]
-4 4.75
5.00 VCL - Supply voltage [V]
5.25
Supply voltage (VCL) vs. Differential gain (DGCCD)
5 2.5
Supply voltage (VCL) vs. Output pin voltage (Vdo1)
DGCCD - Differential gain [%]
4
3
Vdo1 - Output pin voltage [V]
5.25
2.0
2
1
0 4.75
5.00 VCL - Supply voltage [V]
1.5 4.75
5.00 VCL - Supply voltage [V]
5.25
Supply voltage (VDD) vs. Insert gain (IGCCD)
2 1
Supply voltage (VDD) vs. Frequency characteristics (fCCD)
fCCD - Frequency characteristics [dB]
9.5
1
0
IGCCD - Insert gain [dB]
0
-1
-1
-2
-2
-3
-3 8.5
9.0 VDD - Supply voltage [V]
-4 8.5
9.0 VDD - Supply voltage [V]
9.5
- 11 -
CXL1008M/P
Supply voltage (VDD) vs. Differential gain (DGCCD)
5 2.5
Supply voltage (VDD) vs. Output pin voltage (Vdo1)
DGCCD - Differential gain [%]
4
3
Vdo1 - Output pin voltage [V]
9.0 VDD - Supply voltage [V]
2.0
2
1
0 8.5
9.5
1.5 8.5
9.0 VDD - Supply voltage [V]
9.5
Ambient temperature (Ta) vs. Insert gain (IGCCD)
2 1
Ambient temperature (Ta) vs. Frequency characteristics (fCCD)
fCCD - Frequency characteristics [dB]
IGCCD - Insert gain [dB]
1
0
0
-1
-1
-2
-2
-3
-3
0 20 40 60 Ta - Ambient temperature [C]
-4
0 20 40 60 Ta - Ambient temperature [C]
Ambient temperature (Ta) vs. Differential gain (DGCCD)
5 2.5
Ambient temperature (Ta) vs. Output pin voltage (Vdo1)
DGCCD - Differential gain [%]
4
3
Vdo1 - Output pin voltage [V]
0 20 40 60 Ta - Ambient temperature [C]
2.0
2
1
0
1.5
0 20 40 60 Ta - Ambient temperature [C]
- 12 -
CXL1008M/P
Package Outline CXL1008M
Unit: mm
28PIN SOP (PLASTIC)
+ 0.4 18.8 - 0.1 28 15 0.15 + 0.2 0.1 - 0.05 + 0.4 2.3 - 0.15
10.3 0.4
+ 0.3 7.6 - 0.1
9.3
1 0.45 0.1
14
1.27
+ 0.1 0.15 - 0.05
0.24
M
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SOP-28P-L02 SOP028-P-0375 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 0.6g
CXL1008P
28PIN DIP (PLASTIC)
+ 0.1 0.05 0.25 -
15
+ 0.4 37.8 - 0.1
28
+ 0.3 13.0 - 0.1
0.5 0.2
1 2.54
14
0.5 0.1 1.2 0.15
Two kinds of package surface: 1.All mat surface type. 2.Center part is mirror surface.
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING COPPER ALLOY 4.2g
SONY CODE EIAJ CODE JEDEC CODE
DIP-28P-03 DIP028-P-0600
- 13 -
3.0 MIN
0.5 MIN
LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
+ 0.4 4.6 - 0.1
15.24
0 to 15

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